The present invention relates to a semiconductor integrated circuit using SOI (Silicon On Insulator) type field effect transistors (called MOS transistors in the present specification), and particularly to a power shutdown technique thereof.
In a bulk type MOS integrated circuit, active regions are formed in a substrate and well regions to configure MOS transistors. In an SOI type MOS integrated circuit, however, a large number of active regions are formed in an insulating thin film provided on a substrate, without using the well regions, and MOS transistors are configured in the individual active regions. Thus, the SOI type MOS integrated circuit is fundamentally different from the bulk type MOS integrated circuit in terms of device isolation. There are little junction capacitance and junction leak between the same circuit and the substrate. In this respect, the SOI type MOS integrated circuit is superior to the bulk type MOS integrated circuit in terms of a low voltage operation, low power consumption and a high-speed operation. From the viewpoint of the low power consumption and the high-speed operation, a patent document 1 (Japanese Unexamined Patent Publication No. Hei 8(1996)-228145) illustrates by way of example, a configuration wherein the bodies of MOS transistors constituting a logic circuit are respectively set to a low threshold voltage by bringing them into floating, and the MOS transistors constituting the logic circuit are brought into a high threshold voltage by body-biasing a power supply switch connected to a power supply and ground respectively. According to this example, a high-speed operation of the logic circuit can be attained by the MOS transistors low in threshold voltage, and low power consumption at standby can be achieved by the power supply switch high in threshold voltage. A patent document 2 (Japanese Unexamined Patent Publication No. Hei 9(1997)-121152) describes that the body of a power supply switch is biased by its own gate potential thereby to realize the setting of a variable threshold voltage to the power supply switch. When the power supply switch is in an on state, current supply capability can be obtained by bringing the power supply switch to a low threshold voltage. Further, when the power supply switch is in an off state, a subthreshold leak current is reduced by bringing the power supply switch to a high threshold voltage. A backbias technique that an input terminal of a CMOS inverter is connected to its body has been described in the patent document 2.